3D memory array with read bit line shielding
US8982622B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Oct 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.