Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memory
US8982637B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2013 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Sep 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.