Precise data return handling in speculative processors
US8984264B2 · kind B2 · utility
34Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2010 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | Nov 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.