Uniform gate height for semiconductor structure with N and P type fins

US8987083B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Zhenyu Hu · Leonberg, DE
• Zhao Lun · Singapore, SG
• Xing Zhang · Hefei, CN

Key dates

• Filing date: Mar 10, 2014
• Grant date: Mar 24, 2015
• Expiry date: Mar 10, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.