Prevention of faceting in epitaxial source drain transistors
US8987827B2 · kind B2 · utility
5Cited by
1References
44Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 31, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | May 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.