Method of fabricating isolating semiconductor structures using a layout of trenches and openings

US8994127B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thoralf Kautzsch · Dresden, DE
• Boris Binder · Dresden, DE
• Torsten Helm · Rabenau, DE
• Stefan Kolb · Unterschleißheim, DE
• Marc Probst · Radeberg, DE
• Uwe Rudolph · Dresden, DE

Key dates

• Filing date: Nov 24, 2011
• Grant date: Mar 31, 2015
• Expiry date: Feb 23, 2033

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B81C2201/0116
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted.