Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US8994185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Oct 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.