Inventor · Singapore, SG

Kang Chen

120Patents
19h-index
33Co-inventors
86Inventor score

Filing activity: Jan 15, 2002 → May 24, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8193604B2 Semiconductor package with semiconductor core structure and method of forming the same Electricity 136 Active
US7642128B1 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Electricity 97 Active
US8796846B2 Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSP Electricity 95 Active
US9385006B2 Semiconductor device and method of forming an embedded SOP fan-out package Electricity 62 Active
US9082806B2 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Electricity 60 Active
US7772081B2 Semiconductor device and method of forming high-frequency circuit structure and method thereof Electricity 56 Active
US7691747B2 Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures Electricity 53 Active
US9679863B2 Semiconductor device and method of forming interconnect substrate for FO-WLCSP Electricity 52 Active
US9064936B2 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Electricity 50 Active
US7858441B2 Semiconductor package with semiconductor core structure and method of forming same Electricity 44 Active
US8810024B2 Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units Electricity 44 Active
US10297518B2 Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package Electricity 43 Active
US8994185B2 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP Electricity 39 Active
US8592992B2 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP Electricity 28 Active
US9842798B2 Semiconductor device and method of forming a PoP device with embedded vertical interconnect units Electricity 28 Active
US7790503B2 Semiconductor device and method of forming integrated passive device module Electricity 22 Active
US8445323B2 Semiconductor package with semiconductor core structure and method of forming same Electricity 22 Active
US9527723B2 Semiconductor device and method of forming microelectromechanical systems (MEMS) package Electricity 20 Active
US8168470B2 Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound Emerging Cross-Sectional Technologies 19 Active
US10049964B2 Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units Electricity 16 Active
US9368563B2 Semiconductor device including integrated passive device formed over semiconductor die with conductive bridge and fan-out redistribution layer Electricity 15 Active
US9685350B2 Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB Electricity 13 Active
US8445990B2 Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor die Electricity 13 Active
US8343809B2 Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die Electricity 13 Active
US9548240B2 Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package Electricity 12 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.