Method for providing vias
US8999184B2 · kind B2 · utility
1Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Aug 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming via holes in an etch layer disposed below a patterned organic mask with a plurality of patterned via holes is provided. The patterned organic mask is treated by flowing a treatment gas comprising H2. A plasma is formed from the treatment gas. The patterned via holes are rounded to form patterned rounded via holes by exposing the patterned via holes to the plasma. The flow of the treatment gas is stopped. The plurality of patterned rounded via holes are transferred into the etch layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.