Method for forming fine pattern of semiconductor device using double spacer patterning technology
US8999848B2 · kind B2 · utility
21Cited by
3References
8Claims
0Family size
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Key dates
| Filing date | Nov 16, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jan 1, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.