Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

US9003125B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ekaterina M. Ambroladze · Los Angeles, US
• Michael A. Blake · Wappingers Falls, US
• Tim Bronson · Round Rock, US
• Garrett M. Drapala · Poughkeepsie, US
• Pak-kin Mak · Poughkeepsie, US
• Arthur J. O'Neill · Poughkeepsie, US

Key dates

• Filing date: Jun 14, 2012
• Grant date: Apr 7, 2015
• Expiry date: Dec 28, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0859
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.