Methods to produce high density, multilayer printed wiring boards from parallel-fabricated circuits and filled vias
US9003648B2 · kind B2 · utility
3Cited by
12References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2007 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Dec 31, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/1056
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention provides methods to mass laminate and interconnect high density interconnect circuit layers fabricated through parallel processing. Invention methods employ an inside-out interconnection strategy that eliminates plating of vias and provides defect-free outer circuit layers. Conductive paste and via layers are also key features of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.