Self aligned device with enhanced stress and methods of manufacture
US9006052B2 · kind B2 · utility
1Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2010 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
Abstract
A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.