Tuning strain in semiconductor devices
US9006842B2 · kind B2 · utility
23Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jul 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.