Through silicon via with reduced shunt capacitance
US9006846B2 · kind B2 · utility
18Cited by
68References
8Claims
0Family size
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Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Oct 14, 2031 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B2207/096
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.