Layer stack
US9006899B2 · kind B2 · utility
0Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2012 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Dec 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.