Dual side package on package
US9006904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2012 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/1053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.