Reducing memory refresh exit time
US9007862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jul 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.