Method and apparatus to implement lazy flush in a virtually tagged cache memory

US9009413B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Varun K. Mohandru · Braunschweig, DE
• Fernando Latorre · Soria, ES
• Niranjan L. Cooray · Folsom, US
• Pedro Lopez · Molins de Rei, ES
• Naveen Neelakantam · Mountain View, US
• Li-Gao Zei · Braunschweig, DE
• Rami May · Haifa, IL
• Jaroslaw Topp
• Thomas Gaertner · Sheffield, GB

Key dates

• Filing date: Dec 21, 2012
• Grant date: Apr 14, 2015
• Expiry date: Aug 8, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/1036
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.