Pedro Lopez
22Patents
8h-index
52Co-inventors
74Inventor score
Filing activity: Oct 27, 2006 → May 3, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10151181B2 | Selectable switch to set a downhole tool | Fixed Constructions | 36 | Active |
| US9978014B2 | Reconfigurable processing unit | Physics | 20 | Active |
| US9613001B2 | Processing device for performing convolution operations | Physics | 16 | Active |
| US9971540B2 | Storage device and method for performing convolution operations | Physics | 16 | Active |
| US7895415B2 | Cache sharing based thread control | Physics | 14 | Active |
| US8612698B2 | Replacement policy for hot code detection | Physics | 14 | Active |
| US8261046B2 | Access of register files of other threads using synchronization | Physics | 11 | Active |
| US8909902B2 | Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution | Physics | 8 | Active |
| US9280474B2 | Adaptive data prefetching | Physics | 7 | Active |
| US9158705B2 | Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset | Physics | 4 | Active |
| US9940138B2 | Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations | Physics | 4 | Active |
| US9811341B2 | Managed instruction cache prefetching | Physics | 3 | Active |
| US10002108B2 | Processing device for performing convolution operations | Physics | 2 | Active |
| US10621092B2 | Merging level cache and data cache units having indicator bits related to speculative execution | Physics | 1 | Active |
| US9009413B2 | Method and apparatus to implement lazy flush in a virtually tagged cache memory | Physics | 1 | Active |
| US10013326B2 | Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region | Physics | 1 | Active |
| US10997273B2 | Method and apparatus for distributed and cooperative computation in artificial neural networks | Emerging Cross-Sectional Technologies | 1 | Active |
| US11281965B2 | Reconfigurable processing unit | Physics | 0 | Active |
| US10402468B2 | Processing device for performing convolution operations | Physics | 0 | Active |
| US12032653B2 | Method and apparatus for distributed and cooperative computation in artificial neural networks | Emerging Cross-Sectional Technologies | 0 | Active |
| US10157063B2 | Instruction and logic for optimization level aware branch prediction | Physics | 0 | Active |
| US9507725B2 | Store forwarding for data caches | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.