Method for fabricating semiconductor device with vertical transistor structure
US9012303B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Oct 21, 2014 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Oct 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.