Through silicon via process
US9012324B2 · kind B2 · utility
8Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2012 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Aug 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.