III-V semiconductor structures and methods for forming the same

US9012919B2 · kind B2 · utility

Assignee

• SOITEC · FR

Inventors

• Ed Lindow · Scottsdale, US
• Chantal Arena · Mesa, US
• Ronald Thomas Bertram, JR. · Mesa, US
• Ranjan Datta · Bengaluru, IN
• Subhash Mahajan · Tempe, US

Key dates

• Filing date: Jan 10, 2013
• Grant date: Apr 21, 2015
• Expiry date: Apr 10, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.