1T MIM memory for embedded RAM application in soc
US9012967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2012 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Feb 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.