Semiconductor package with improved pillar bump process and structure
US9013037B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2011 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Dec 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.