DRAM with pulse sense amp
US9013941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.