Vertical oxide-oxide interface for forming-free, low power and low variability RRAM devices
US9018037B1 · kind B1 · utility
6Cited by
4References
12Claims
0Family size
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Key dates
| Filing date | Dec 5, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Dec 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
Abstract
Forming a resistive switching layer having a vertical interface can generate defects confined along the interface between two electrodes. The confined defects can form a pre-determined region for filament formation and dissolution, leading to low power resistive switching and low program voltage or current variability. In addition, the filament forming process of the resistive memory device can be omitted due to the existence of the confined defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.