Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer
US9018057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Jan 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.