Inventor · Guilderland, NY, US

Qing Liu

198Patents
13h-index
58Co-inventors
89Inventor score

Filing activity: Oct 7, 1997 → Feb 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9502518B2 Multi-channel gate-all-around FET Electricity 40 Active
US8878300B1 Semiconductor device including outwardly extending source and drain silicide contact regions and related methods Electricity 34 Active
US9466452B1 Integrated cantilever switch Electricity 26 Active
US9202920B1 Methods for forming vertical and sharp junctions in finFET structures Electricity 25 Active
US9748352B2 Multi-channel gate-all-around FET Electricity 24 Active
US9391200B2 FinFETs having strained channels, and methods of fabricating finFETs having strained channels Electricity 24 Active
US8975168B2 Method for the formation of fin structures for FinFET devices Electricity 19 Active
US9082852B1 LDMOS FinFET device using a long channel region and method of manufacture Electricity 19 Active
US9793395B1 Vertical vacuum channel transistor Electricity 17 Active
US9748369B2 Lateral bipolar junction transistor (BJT) on a silicon-on-insulator (SOI) substrate Electricity 14 Active
US9281382B2 Method for making semiconductor device with isolation pillars between adjacent semiconductor fins Electricity 14 Active
US9202919B1 FinFETs and techniques for controlling source and drain junction profiles in finFETs Electricity 13 Active
US9515185B2 Silicon germanium-on-insulator FinFET Electricity 13 Active
US8828851B2 Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering Electricity 12 Active
US9466722B2 Large area contacts for small transistors Electricity 10 Active
US9299721B2 Method for making semiconductor device with different fin sets Electricity 10 Active
US9012999B2 Semiconductor device with an inclined source/drain and associated methods Electricity 10 Active
US9263338B2 Semiconductor device including vertically spaced semiconductor channel structures and related methods Electricity 10 Active
US9219078B2 Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs Electricity 10 Active
US9018057B1 Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer Electricity 9 Active
US6108412A Adaptive echo cancelling system for telephony applications Electricity 9 Expired
US9093556B2 Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods Electricity 9 Active
US9607901B2 Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology Electricity 9 Active
US8750528B2 Audio apparatus and audio controller thereof Electricity 9 Active
US9105691B2 Contact isolation scheme for thin buried oxide substrate devices Electricity 9 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.