Method of making a 3D integrated circuit
US9018078B2 · kind B2 · utility
3Cited by
1References
20Claims
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Key dates
| Filing date | Jan 28, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.