Tapered fin field effect transistor

US9018084B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Michael A. Guillorn · Locke, US
• Chung-Hsun Lin · White Plains, US
• Ryan M. Martin · New York, US
• Jeffrey W. Sleight · Ridgefield, US

Key dates

• Filing date: Sep 9, 2013
• Grant date: Apr 28, 2015
• Expiry date: Sep 19, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P80/30
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.