Multiple step anneal method and semiconductor formed by multiple step anneal
US9018089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2011 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Dec 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.