Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates
US9018094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2011 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Oct 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.