Memory management unit tag memory
US9021194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2011 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.