Shared error protection for register banks
US9021328B2 · kind B2 · utility
1Cited by
69References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Mar 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2909
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.