Three-dimensional memory and method of forming the same
US9023701B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Dec 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A method of forming a three-dimensional memory is provided. A stacked structure is patterned to form a comb structure including a bit line pad extending along a first direction and comb-teeth portions extending along a second direction. A charge storage layer is formed on top and sidewall of the comb structure. Bit lines and auxiliary gates are formed on the charge storage layer and extend along the first direction. Each bit line covers top and sidewall of partial comb-teeth portions. Auxiliary gates cover top and sidewall of edge regions of the bit line pad. The charge storage layer on top of the bit line pad is removed. The stacked structure of the bit line pad is patterned to form a stepped structure. An ion implantation is performed to the stepped structure, to form a doped region in the semiconductor layer below each step surface of the stepped structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.