High aspect ratio memory hole channel contact formation

US9023719B2 · kind B2 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventors

• Jayavel Pachamuthu · Milpitas, US
• Johann Alsmeier · San Jose, US
• Raghuveer S. Makala · Campbell, US
• Yao-Sheng Lee · Tampa, US

Key dates

• Filing date: Mar 25, 2014
• Grant date: May 5, 2015
• Expiry date: Mar 25, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.