Fin-type transistor structures with extended embedded stress elements and fabrication methods
US9024368B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Nov 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.