Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

US9024657B2 · kind B2 · utility

Assignee

• eASIC CORPORATION · US

Inventors

• Alexander E. Andreev · San Jose, US
• Ranko Scepanovic · San Jose, US
• Ivan Pavisic · Cupertino, US
• Alexander Yahontov · Moskovskiy, RU
• Mikhail Udovikhin · Moskovskiy, RU
• Igor Vikhliantsev · San Jose, US
• Chong-Teik Lim · Bukit Mertajam, MY
• Seow-Sung Lee · Bukit Mertajam, MY
• Chee-Wei Kung · Bukit Mertajam, MY

Key dates

• Filing date: Oct 11, 2012
• Grant date: May 5, 2015
• Expiry date: Feb 14, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.