Non-volatile memory device with clustered memory cells
US9025355B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 30, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Jul 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.