Memory disturb reduction for nonvolatile memory
US9025375B2 · kind B2 · utility
4Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | Oct 22, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Oct 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.