Pre-conditioning circuits and methods for programmable impedance elements in memory devices
US9025396B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Mar 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a plurality of programmable impedance elements programmable between a low impedance state in response to a program voltage and a higher impedance state in response to an erase voltage having a different polarity than the program voltage; a programming circuit configured to apply the program and erase voltages to selected elements; and a pre-condition path configured to apply a pre-condition voltage only of the erase voltage polarity to fresh elements in a pre-condition operation; wherein fresh elements are elements that have not been subject to any programming voltages. The pre-condition electrical conditions can also include high voltage low current conditions that apply a greater magnitude voltage and smaller current than the first or second electrical conditions, or high voltage low current conditions that apply a greater magnitude voltage and greater current than the first or second electrical conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.