Interrupt processing unit for preventing interrupt loss
US9026705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2012 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Jul 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element. In some embodiments, the corrective action may include altering the power state of the first processing element such that it becomes available to receive interrupts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.