Memory with word level power gating
US9026808B2 · kind B2 · utility
5Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2012 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Apr 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.