Method of fabricating semiconductor package
US9029203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.