Semiconductor device and method of forming the device by forming monocrystalline semiconductor layers on a dielectric layer over isolation regions
US9029229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2013 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Jul 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/821
Abstract
Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.