Transistor performance using a two-step damage anneal
US9029251B2 · kind B2 · utility
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3Claims
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Key dates
| Filing date | Aug 5, 2014 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | Aug 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/314
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.