Using wafer geometry to improve scanner correction effectiveness for overlay control
US9029810B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2014 |
| Grant date | May 12, 2015 |
| Priority date | — |
| Expiry date | May 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31701
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Systems and methods for providing improved scanner corrections are disclosed. Scanner corrections provided in accordance with the present disclosure may be referred to as wafer geometry aware scanner corrections. More specifically, wafer geometry and/or wafer shape signature information are utilized to improve scanner corrections. By removing the wafer geometry as one of the error sources that may affect the overlay accuracy, better scanner corrections can be obtained because one less contributing factor needs to be modeled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.