Planar resistive memory integration

US9029827B2 · kind B2 · utility

Assignee

• UNITY SEMICONDUCTOR · US

Inventors

• Lidia Vereen · San Ramon, US
• Bruce L. Bateman · Fremont, US
• Louis C. Parrillo · Austin, US
• Elizabeth Friend · Sunnyvale, US
• David Eggleston · San Jose, US

Key dates

• Filing date: Oct 24, 2013
• Grant date: May 12, 2015
• Expiry date: Oct 24, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.