Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer

US9029919B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stephan Kronholz · Dresden, DE
• Joachim Patzer · Rohrbach, DE

Key dates

• Filing date: Feb 1, 2013
• Grant date: May 12, 2015
• Expiry date: Jun 21, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.